Command-line options

Command-line options can select startup preferences, run a project without the graphical interface, or invoke verification and FPGA workflows. The general syntax is:

java -jar jarFileName [options] [project-files]

Project files that are not consumed as option arguments are opened by Logisim-evolution. Long option names are shown below; where available, the equivalent short name is shown first. For example:

java -jar jarFileName --user-template plain --gates ansi --locale en

General options

-h, --help

Displays the current command-line option summary and exits.

-v, --version

Displays version and build information and exits.

--clear-prefs

Clears saved application preferences at startup.

-g, --gates [ansi|iec]

Selects ANSI-shaped or IEC-rectangular gate symbols.

-m, --geometry WIDTHxHEIGHT[+X+Y]

Sets the main-window dimensions and, when supplied, the position of its upper-left corner. For example: --geometry 600x400+100+100.

-o, --locale LANGUAGE

Selects one of the supported locale identifiers:

de German

el Greek

en English

es Spanish

fr French

pt Portuguese

ru Russian

it Italian

nl Dutch

ja Japanese

pl Polish

zh Simplified Chinese

-u, --user-template [empty|plain|FILE]

Selects the empty template, the default plain template, or a readable custom template file.

--no-splash

Hides the splash screen at startup.

-s, --substitute LIBRARY1 LIBRARY2

Replaces references to LIBRARY1 with LIBRARY2 while loading projects. See Substituting libraries.

TTY simulation options

-t, --tty FORMAT[,FORMAT...]: Runs without the graphical interface. Accepted comma-separated formats are table, speed, tty, halt, stats, binary, hex, csv, and tabs. See Other verification options.
-l, --load FILE [LABEL]: Loads a memory image before a TTY simulation. With a label, it applies to matching RAM and ROM components; without one, it supplies the fallback image. The option may be repeated for different labels and works only with --tty.
--save FILE: Saves RAM contents to an image file after a TTY run. This option works only with --tty.
--toplevel-circuit NAME: Selects the circuit to use as the top-level circuit.

Verification and conversion options

-w, --test-vector CIRCUIT VECTOR_FILE PROJECT_FILE: Runs VECTOR_FILE against CIRCUIT in PROJECT_FILE, then exits. See Test vectors.
-b, --test-circuit CIRC_FILE: Opens a project, runs its test bench, reports success or failure, and exits.
-n, --new-file-format INPUT OUTPUT: Opens INPUT as a Logisim project and writes it to OUTPUT using the current Logisim-evolution file format.

FPGA options

-f, --test-fpga CIRC_FILE CIRCUIT BOARD [TICK_FREQUENCY] [HDLONLY]: Runs the FPGA implementation flow for CIRCUIT on BOARD. The optional tick frequency is in hertz. HDLONLY stops after HDL generation; the two optional values may be supplied in either order.
--fpga-cable NAME: Selects an Intel/Altera Quartus cable by its exact reported name. This option requires --test-fpga and is only valid for Intel/Altera targets.

Next: User's Guide.